Spread spectrum technology is a cost effective method to reduce Electromagnetic Interference (EMI) in the PC motherboard. Effectively shaping noise, delta-sigma (Δ-Σ) technology is adopted by most digital spread spectrum implementations in SSCG. At higher spectrum amplitudes, the SSCG performs well. However, when reducing the spectrum amplitude, its performance can become increasingly worse.
For traditional implementations, to improve the performance of the SSCG, a higher resolution of Δ-Σ is needed. For example, an output source providing a higher timing accuracy can improve the performance. Increasing the operation frequency is a known option, but it can be limited by the maximum allowed operation frequency and power consumption of the device.
For spread spectrum solutions based on a PLL, a frequency divider can be used for generating the source timing. Using an integer-N counter with known solutions, the resolution of the divider is inversely proportional to the frequency of the input clock (e.g., higher resolution can be obtained by a higher work frequency) if the frequency of the output clock is fixed. For the traditional Δ-Σ application, the minimum step of the divisors is 2 because the closest two divisors must be N+1 and N−1 (2=N+1−(N−1)). Because of this large minimum step, the resolution of the output spread clock is affected, thereby providing a less accurate output spread clock.